FIG. 1 is a view illustrating one example of an internal process of a transmitter P100. The transmitter P100 is an apparatus for performing frame transmission, e.g., in a network of a carrier. The transmitter P100 includes, for example, a plurality of line interface unit (LIU) cards P1, a back wire board (BWB) P3 and a control card (not illustrated). Each LIU card P1 is an interface card. The BWB P3 is a switch card which interconnects LIUs in a full mesh. The control card controls the LIU cards P1 and the BWB P3.
Each LIU card P1 includes a plurality of field programmable gate arrays (FPGAs). In the example illustrated in FIG. 1, the FPGAs included in each LIU card P1 are a forward FPGA P103B, a policer FPGA P103C, a BWB interface FPGA P103D and a shaper FPGA P103E. The FPGAs are integrated circuits for executing their respective programmed processes.
A frame input to the transmitter P100 is processed and transmitted by each FPGA in each LIU card P1. An in-device header is added to the frame input to the transmitter P100. The in-device header is information used to process an output port or each FPGA in the transmitter P100 of the frame and includes information referred to by each card in the transmitter P100. Each FPGA processes the frame by referring to the in-device header, rewrites the in-device header and transmits the frame.
FIG. 2 is a view illustrating one example of an error detecting process in an LIU card P1. Each FPGA in the LIU card P1 adds an error detection code to a frame output to a FPGA at the next stage. The next stage FPGA calculates an error detection code from the input frame and checks whether or not the calculated error detection code matches the error detection code added to the input frame. If the calculated error detection code does not match the error detection code added to the input frame, data abnormality such as a bit error or the like in transmission between FPGAs is detected.
For example, as an error detection code, FCS (Frame Check Sequence) is used between an MAC/PHY circuit P103A and the forward FPGA P103B, and between the shaper FPGA P103E and the MAC/PHY circuit P103A. For example, as an error detection code, BIP (Bit Interleaved Parity) is used between the forward FPGA P103B and the policer FPGA P103C, between the policer FPGA P103C and the BWB interface FPGA P103D, between the BWB interface FPGA P103D and the forward FPGA P103B, and between the forward FPGA P103B and the shaper FPGA P103E.
Related technologies are disclosed in, for example, Japanese Laid-Open Patent Publication No. 2009-278576, Japanese Laid-Open Patent Publication No. 2002-064490, and Japanese Laid-Open Patent Publication No. 2011-146774.